(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to integrate the fabrication of a high voltage double diffused drain (DDD) metal oxide semiconductor field effect transistor (MOSFET) with the fabrication of low voltage deep sub-micron complimentary metal oxide semiconductor (CMOS) devices.
(2) Description of Prior Art
High voltage transistors used for applications between abut 12 to 25 volts, have been fabricated featuring double diffused drains (DDD). To obtain the doubled diffused drain element high ion implantation energies are required. However if the fabrication of high voltage devices are to be integrated with the fabrication of low voltage devices special care must be taken to protect the low voltage devices from procedures required for the DDD components, procedures such as high energy ion implantation steps. In addition to requiring a high energy ion implantation procedure the high voltage devices also require more robust thermal cycles than the low voltage counterparts to achieve the desired DDD depth. The high voltage DDD devices also require a specific thickness of conductive gate structure needed to block the high energy ion implantation step, however if thicker conductive gate structures were also used for narrower gate low voltage devices patterning difficulties can arise as a result of unacceptable high aspect ratios. Therefore a unique process sequence is needed to integrate the fabrication of high voltage devices featuring a double diffused drain, with the fabrication of low voltage device.
The present invention will describe a novel process sequence in which the integration of high voltage and low voltage devices are successfully integrated featuring a process which allows only the device double diffused drain high voltage devices to experience the high energy ion implanted drain procedure, a specific robust thermal cycle, and to be comprised with a thickness of a composite conductive gate structure needed to protect the channel region from the high energy ion implantation procedure. Prior art such as Wu in U.S. Pat. No. 6,570,214 B1, Liu in U.S. Pat. No. 6,333,234 B1, Chu in U.S. Pat. No. 6,297,108 B1, and Su et al in U.S. Pat. No. 6,133,096,describe procedures for fabricating, and integrating DDD devices, however none of the above prior art describe the novel process sequence described in the present invention for integration of high voltage and low voltage devices.